1. Field of the Invention
The invention relates to a method of fabricating gate oxide layer with different thicknesses, and more particularly to a method of fabricating gate oxide layer with different thicknesses, which can provide improved protection against electrostatic discharge (ESD).
2. Description of the Related Art
As the size of semiconductor technology becomes smaller and smaller, the length of the channel becomes shorter. When the length of the channel becomes small, the across-electric field in the channel increases if the voltage applied on the gate doesn't change. The energy of the electrons in the channel increases because the electric field increases and the energy of the electrons is higher, especially adjacent to the channel and the drain region. The energy of the electrons is higher than the other electrons that are in thermal equilibrium, so the electrons are called hot electrons. The phenomenon is called the hot electron effect and it is also called the hot carrier effect. The hot electron effect affects the operation of the MOS transistor because the channel length has shortened.
One method of solving the hot electron effect of short channel length, for example, is to decrease the operation voltage of MOS transistor. Another method used is to construct a lightly doped drain (LDD). In the lightly doped drain method a doped region is formed near the original MOS source/drain region, adjacent to the channel, and the dosage of the LDD is lighter than the original source/drain region.
The capacity of electrostatic-discharge protection is affected by using the LDD structure. Static voltage can be produced by walking across a room or by removing an integrated circuit from its plastic package. If such a high voltage is accidentally applied to the pins of an IC package, its discharge can cause breakdown of the gate oxide of the devices to which it is applied. The breakdown event may cause sufficient damage to produce immediate destruction of the devices, or it may weaken the oxide enough that it will fail early in the operating life of the device.
Therefore, all pins of MOS integrated circuits must be provided with protection circuits to prevent such voltages from damaging the MOS gates. These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting or to undergo breakdown, thereby providing an electrical path to a ground. Since the breakdown mechanism is designed to be nondestructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals.